1. Field of the Invention
The present invention relates to a thin film magnetic memory device. More particularly, the present invention relates to a random access memory (RAM) including memory cells having a magnetic tunnel junction (MTJ).
2. Description of the Background Art
An MRAM (Magnetic Random Access Memory) device has attracted attention as a memory device capable of non-volatile data storage with low-power consumption. The MRAM device is a memory device that stores data in a non-volatile manner a plurality of thin film magnetic elements formed in a semiconductor integrated circuit and is capable of random access to each thin film magnetic element.
In particular, recent announcement shows that significant progress in performance of the MRAM device is achieved by using thin film magnetic elements having a magnetic tunnel junction (MTJ) as memory cells. The MRAM device including memory cells having a magnetic tunnel junction is disclosed in technical documents such as “A ions Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, February 2000, and “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, February 2000.
FIG. 88 is a schematic diagram showing the structure of a memory cell having a magnetic tunnel junction (hereinafter, also simply referred to as “MTJ memory cell”).
Referring to FIG. 88, the MTJ memory cell includes a magnetic tunnel junction MTJ having its resistance value varied according to the level of storage data, and an access transistor ATR. The access transistor ATR is formed by a field effect transistor, and is coupled between the magnetic tunnel junction MTJ and ground voltage Vss.
For the MTJ memory cell are provided a write word line WWL for instructing a data write operation, a read word line RWL for instructing a data read operation, and a bit line BL serving as a data line for transmitting an electric signal corresponding to the level of storage data in the data read and write operations.
FIG. 89 is a conceptual diagram illustrating the data read operation from the MTJ memory cell.
Referring to FIG. 89, the magnetic tunnel junction MTJ has a magnetic layer FL having a fixed magnetic field of a fixed direction (hereinafter, also simply referred to as “fixed magnetic layer FL”), and a magnetic layer VL having a free magnetic field (hereinafter, also simply referred to as “free magnetic layer VL”). A tunnel barrier TB formed from an insulator film is provided between the fixed magnetic layer FL and free magnetic layer VL. According to the level of storage data, either a magnetic-field of the same direction as that of the fixed magnetic layer FL or a magnetic field of the direction different from that of the fixed magnetic layer FL is written to the free magnetic layer VL in a non-volatile manner.
In reading the data, the access transistor ATR is turned ON in response to activation of the read word line RWL. As a result, a sense current Is flows through a current path formed by the bit line BL, magnetic tunnel junction MTJ, access transistor ATR and ground voltage Vss. The sense current Is is supplied as a constant current from a not-shown control circuit.
The resistance value of the magnetic tunnel junction MTJ varies according to the relative relation of the magnetic field direction between the fixed magnetic layer FL and free magnetic layer VL. More specifically, in the case where the fixed magnetic layer FL and free magnetic layer VL have the same magnetic field direction, the magnetic tunnel junction MTJ has a smaller resistance value as compared to the case where both magnetic layers have different magnetic field directions.
Accordingly, in reading the data, a voltage level change at the magnetic tunnel junction MTJ due to the sense current Is varies according to the magnetic field direction stored in the free magnetic layer VL. Thus, by starting supply of the sense current Is after precharging the bit line BL to a prescribed voltage, the level of storage data in the MTJ memory cell can be read by monitoring a voltage level change on the bit line BL.
FIG. 90 is a conceptual diagram illustrating the data write operation to the MTJ memory cell.
Referring to FIG. 90, in writing the data, the read word line RWL is inactivated, and the access transistor ATR is turned OFF. In this state, a data write current for writing a magnetic field to the free magnetic layer VL is applied to the write word line WWL and bit line BL. The magnetic field direction of the free magnetic layer VL is determined by combination of the respective directions of the data write current flowing through the write word line WWL and bit line BL.
FIG. 91 is a conceptual diagram illustrating the relation between the respective directions of the data write current and magnetic field in the data write operation.
Referring to FIG. 91, a magnetic field Hx of the abscissa indicates the direction of a magnetic field H(WWL) produced by the data write current flowing through the write word line WWL. A magnetic field Hy of the ordinate indicates the direction of a magnetic field H(BL) produced by the data write current flowing through the bit line BL.
The magnetic field direction stored in the free magnetic layer VL is updated only when the sum of the magnetic fields H(WWL) and H(BL) reaches the region outside the asteroid characteristic line shown in the figure. In other words, the magnetic field direction stored in the free magnetic layer VL is not updated when a magnetic field corresponding to the region inside the asteroid characteristic line is applied.
Accordingly, in order to update the storage data of the magnetic tunnel junction MTJ by the data write operation, a current must be applied to both the write word line WWL and bit line BL. Once the magnetic field direction, i.e., the storage data, is stored in the magnetic tunnel junction MTJ, it is held therein in a non-volatile manner until a new data read operation is conducted.
The sense current Is flows through the bit line BL even in the data read operation. However, the sense current Is is generally set to a value that is smaller than the above-mentioned data write current by about one or two orders of magnitude. Therefore, it is less likely that the storage data in the MTJ memory cell is erroneously rewritten due to the sense current Is during the data read operation.
The above-mentioned technical documents disclose a technology of forming an MRAM device, a random access memory, with such MTJ memory cells integrated on a semiconductor substrate.
FIG. 92 is a conceptual diagram showing the MTJ memory cells arranged in rows and columns in an integrated manner.
Referring to FIG. 92, with the MTJ memory cells arranged in rows and columns on the semiconductor substrate, a highly integrated MRAM device can be realized. FIG. 92 shows the case where the MTJ memory cells are arranged in n rows by m columns (where n, m is a natural number).
As described before, the bit line BL, write word line WWL and read word line RWL must be provided for each MTJ memory cell. Accordingly, n write word lines WWL1 to WWLn, n read word lines RWL1 to RWLn, and m bit lines BL1 to BLm are required for the n×m MTJ memory cells. In other words, independent word lines must be provided for the read and write operations.
FIG. 93 is a diagram showing the structure of the MTJ memory cell formed on the semiconductor substrate.
Referring to FIG. 93, the access transistor ATR is formed in a p-type region PAR of a semiconductor main substrate SUB. The access transistor ATR has source/drain regions (n-type regions) 110, 120 and a gate 130. The source/drain region 110 is coupled to the ground voltage Vss through a metal wiring formed in a first metal wiring layer M1. A metal wiring formed in a second metal wiring layer M2 is used as the write word line WWL. The bit line BL is formed in a third metal wiring layer M3.
The magnetic tunnel junction MTJ is formed between the second metal wiring layer M2 of the write word line WWL and the third metal wiring layer M3 of the bit line BL. The source/drain region 120 of the access transistor ATR is electrically coupled to the magnetic tunnel junction MTJ through a metal film 150 formed in a contact hole, the first and second metal wiring layers M1 and M2, and a barrier metal 140. The barrier metal 140 is a buffer material for providing electrical coupling between the magnetic tunnel junction MTJ and metal wirings.
As described before, in the MTJ memory cell, the read word line RWL is provided independently of the write word line WWL. In addition, in writing the data, a data write current for generating a magnetic field equal to or higher than a predetermined value must be applied to the write word line WWL and bit line BL. Accordingly, the bit line BL and write word line WWL are each formed from a metal wiring.
On the other hand, the read word line RWL is provided in order to control the gate voltage of the access transistor ATR. Therefore, a current need not be actively applied to the read word line RWL. Accordingly, for the purpose of improving the integration degree, the read word line RWL is conventionally formed from a polysilicon layer, polycide structure, or the like in the same wiring layer as that of the gate 130 without forming an additional independent metal wiring layer.
Since a large number of wirings are required for the data read and write operations, integrating the MTJ memory cells on the semiconductor substrate results in increase in cell size due to the space required for such wirings.
Moreover, in order to integrate the MTJ memory cells, a reduced wiring pitch as well as an increased number of wiring layers are required, causing increase in manufacturing cost due to the complicated manufacturing process.
Furthermore, such increased numbers of wirings and wiring layers necessitate the use of so-called cross-point arrangement, i.e., the arrangement in which the MTJ memory cells are provided on the respective intersections of the word lines and bit lines, thereby making it difficult to ensure a sufficient margin of the read and write operations.
In writing the data, a relatively large data write current must be applied to the bit line BL. Moreover, the direction of the data write current must be controlled according to the level of write data, resulting in complicated circuitry for controlling the data write current.